In order to reduce the power consumption of a logic LSI and a system using the logic LSI, it is effective to control the operating frequencies of the logic LSI. In the case of single-chip microcomputers for embedded applications, there has been provided a sleep function for stopping the clock signal supplied to part of the logic LSI or the whole chip under the control of software. For microprocessors used in personal computers, moreover, a technique for controlling the operating frequencies in the whole system by the use of software commands (OS: Operating System) in a dynamic mode has been employed.
Japanese Patent Laid-Open No. 150137/1985, for example, discloses an arrangement for supplying a CPU with a low-speed clock signal for the execution of a program with low priority by monitoring an address bus within a microcomputer. Further, Japanese Patent Laid-Open No. 286213/1966 discloses an arrangement for selectively supplying a plurality of on-chip modules with a plurality of clock signals different in frequency to be designated by commands, respectively.
Japanese Patents Laid-Open Nos. 168818/1991, 296119/1991 also disclose arrangements for reducing power consumption by monitoring the operation of input/output units such as a keyboard so as to lower the frequency of a clock signal when an idle cycle is detected.